1. Field of the Invention
The present invention relates to the provision of isolation structures between devices of an integrated circuit formed in and on a semiconductor substrate and, more particularly, to the formation of shallow trench isolation structures.
2. Description of the Related Art
A variety of integrated circuits incorporate device isolation structures formed between adjacent semiconductor devices to prevent carriers from traveling through the substrate between the adjacent devices. For example, device isolation structures are conventionally formed between adjacent field effect transistors (FETs) in dense semiconductor circuits such as dynamic random access memories (DRAMs) to reduce charge leakage to and from the charge storage nodes of the FETs. Often, device isolation structures take the form of thick field oxide regions extending below the surface of the semiconductor substrate. The most common early technique for forming a field oxide region is the local oxidation of silicon ("LOCOS") technique. The LOCOS technique, including the various modified LOCOS procedures that have been introduced over the years, have provided effective device isolation at a relatively low cost and with an acceptable level of reliability. The LOCOS technique has various drawbacks, however, including its well known problems related to stress generation and the thin "bird's beak" region formed at the periphery of the LOCOS field isolation structure. Particularly because of the bird's beak problem, the LOCOS field isolation structure is difficult to implement effectively for small device geometries and so must be replaced in high density devices by a more readily scaled device isolation structure.
Shallow trench isolation ("STI") has become a prevalent strategy for device isolation. In STI, a sharply defined trench is formed in the semiconductor substrate by anisotropic etching, generally using a silicon nitride hard mask much like the mask used for LOCOS processing. The trench is then filled with oxide to provide a device isolation structure having an upper surface near or at the original substrate surface. FIG. 1 schematically illustrates a small portion of an integrated circuit device incorporating a shallow trench isolation structure. Devices are provided in and on the P-type surface of a silicon substrate 10 which incorporates a shallow trench isolation structure 12 consisting of a trench etched into the surface of the substrate and filled by chemical vapor deposition (CVD) with oxide. A pair of FET devices 14, 16 formed on either side of the STI structure 12 each include a pair of N-type source/drain regions on either side of a channel region in the substrate and a polysilicon gate electrode separated from the channel region by a gate oxide layer. The shallow trench isolation structure separates the closest source/drain regions of the adjacent FET devices 14, 16 to reduce the level of communication between the two FET devices through the substrate. Shallow trench isolation structures provide effective isolation across their entire width and are readily scaled to small device geometries. In this regard, shallow trench isolation structures are unlike LOCOS isolation regions, which must accommodate the bird's beak structures on either side of the LOCOS isolation region and so do not provide device isolation over their entire width. In addition, the techniques typically used to form shallow trench isolation structures naturally produce a substantially planarized surface over the isolation structure. Formation of the shallow trench isolation structure 12 is now discussed in greater detail with reference to FIGS. 2-12.
FIG. 2 illustrates an early stage in the processing of an integrated circuit device including a shallow trench isolation structure. Silicon substrate 10 is coated with a thermal oxide layer 22 that acts as a pad oxide layer to protect the substrate during processing. Pad oxide layer 22 is generally removed before the final gate oxide layer is formed. A layer of silicon nitride 24 is formed by chemical vapor deposition on the pad oxide layer 22 and then a layer of photoresist is deposited, exposed and etched to form an implantation mask 26 on the surface of the silicon nitride layer 24. Ions are typically implanted into the substrate at this stage of the processing to form an electrical isolation device such as an isolation well having a P/N junction along its boundaries. This implantation might alternatively be performed later in the processing, after the planarization of the trench isolation regions shown in FIGS. 6 and 9. The implantation mask 26 is then removed. Next, a trench definition mask 28 as illustrated in FIG. 3 is formed by depositing a layer of photoresist onto silicon nitride layer 24 and then exposing and etching the photoresist layer to form the mask 28. A trench is formed in the substrate by consecutively etching the silicon nitride layer 24, the pad oxide layer 22, and then etching a trench 30 into the silicon substrate 10 (FIG. 4). The trench etching mask 28 is then removed.
Next, the trench 30 is filled with a layer of silicon oxide 32, for example, by atmospheric pressure chemical vapor deposition (APCVD) using tetraethylorthosiloxane (TEOS) as a source gas. The trench is conventionally overfilled during deposition, as shown in FIG. 5, because TEOS oxide typically requires a densification process and the TEOS oxide layer shrinks during densification. Densification of the TEOS oxide is accomplished at a temperature of approximately 1000.degree. C. for a time period of about 10-30 minutes. After densification, the portion of the TEOS oxide layer extending above the silicon nitride layer 24 is removed by chemical mechanical polishing using the silicon nitride layer 24 as a stop for the polishing process, leaving an oxide plug 34 in the trench region (FIG. 6). Although not shown in FIG. 6, the surface of the oxide plug 34 is typically recessed slightly below the surface of the silicon nitride layer 24 during chemical mechanical polishing because the TEOS oxide plug is softer than the silicon nitride layer. The silicon nitride layer 24 is next removed to expose the pad oxide layer 22, typically leaving a portion of the oxide plug 34 extending above the surface of the pad oxide layer 22 (FIG. 7). A hydrofluoric acid dip is used to remove the pad oxide (FIG. 8). A thickness of the TEOS oxide plug 34 greater than the thickness of the pad oxide layer 22 is removed during this etching process because the TEOS oxide plug 34 is etched more rapidly than the thermal oxide of the pad oxide layer 22.
A sacrificial oxide layer 36 is grown once again on the surface of the substrate 10 to protect the substrate surface from damage. One or more implantations, including one or more channel threshold adjust implantations, are performed as required by the device being formed (FIG. 9). The sacrificial oxide layer 36 is then removed, once again using a hydrofluoric acid dip, resulting in the structure schematically illustrated in FIG. 10. Often, the combined actions of the oxide etching steps illustrated in FIGS. 8 and 10 cause a sufficient amount of the plug oxide 34 to be etched so that the surface of the plug oxide is recessed below the surface of the substrate 10. The overetching condition may be most pronounced at the edges of the oxide plug 34 immediately adjacent the surface of the substrate 10, or the entire surface of the oxide plug may be recessed substantially uniformly below the surface of the substrate. In either case, overetching may cause a "shoulder" portion of the substrate 38 to be exposed and partially etched at the side wall of the trench, or only a thin layer of TEOS oxide may cover the substrate adjacent the side wall of the trench.
Referring now to FIG. 11, a gate oxide layer 40 is next grown thermally over the exposed surface of the substrate 10. As a practical matter, the gate oxide layer 40 is of poor quality with a convex profile at the "shoulder" region 38 of the substrate near the trench isolation structure. A polysilicon layer 42 is then deposited over the surface of the substrate by chemical vapor deposition. Polysilicon layer 42 is typically doped by ion implantation and annealing, and then patterned to form a wiring line 44 such as that shown in FIG. 12. Because the wiring line 44 extends over both the gate oxide layer 40 and the surface of the oxide plug 34, the wiring line also extends over the shoulder region 38 near the sidewall of the trench. Thus, the poor quality gate oxide sometimes formed over shoulder regions 38 is sufficiently thin and poor as to allow for parasitic MOSFET action at the shoulder region. The formation of parasitic MOSFETs or other forms of electrical coupling between the wiring line and the substrate can reduce the turn-on threshold voltage of the transistor channel and can produce the abnormal subthreshold current associated with the "kink" effect.
It is accordingly an object of the present invention to provide a shallow trench isolation structure that provides desirable levels of device isolation, as well as improved reliability for the structures and devices formed adjacent to the trench isolation structure.